Predictive Method of Charge Storage Memory Degradation on a Dedicated 4kb Test Vehicle

This study investigates the variability in HCI (Hot Carrier Injection) degradation within a 4 kb charge storage memory array, manufactured on a dedicated wafer split process. A standard set of experiments is conducted to extract electrical features of the cells before and after stress. A statistical analysis method, based on the Principal Component Analysis (PCA) approach, is introduced to enhance the comprehension of the cell degradation prior to reliability testing. Additionally, a graphical model is developed to identify extrinsic cells in the memory array prior to stress, as well as to assess the overall technology yield. Finally, others classifier models are explored aiming to improve extrinsic cells detection before running the reliability test.

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Publication Details

Journal
IEEE Transactions on Device and Materials Reliability
Published
2025-05-22
DOI
https://doi.org/10.1109/tdmr.2025.3572856
Primary Topic
VLSI and Analog Circuit Testing
Type
article
Field-Weighted Citation Impact
0.00

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article

Predictive Method of Charge Storage Memory Degradation on a Dedicated 4kb Test Vehicle

Madjid Akbal, A. Regnier, M. Bocquet, Joël Metz et al.
IEEE Transactions on Device and Materials Reliability
VLSI and Analog Circuit Testing
article

Predictive Method of Charge Storage Memory Degradation on a Dedicated 4kb Test Vehicle

Madjid Akbal, A. Regnier, M. Bocquet, Joël Metz, Jean‐Michel Portal, V. Della Marca, Brice Arrazat, Jean-Michel Moragues, Olivier Paulet, Thibault Kempf, Khaled Alkema, S.D. Perrin, Martin Arteaga
article en

Abstract

This study investigates the variability in HCI (Hot Carrier Injection) degradation within a 4 kb charge storage memory array, manufactured on a dedicated wafer split process. A standard set of experiments is conducted to extract electrical features of the cells before and after stress. A statistical analysis method, based on the Principal Component Analysis (PCA) approach, is introduced to enhance the comprehension of the cell degradation prior to reliability testing. Additionally, a graphical model is developed to identify extrinsic cells in the memory array prior to stress, as well as to assess the overall technology yield. Finally, others classifier models are explored aiming to improve extrinsic cells detection before running the reliability test.

IEEE Transactions on Device and Materials ReliabilityVol. 25(3)
Centre National de la Recherche Scientifique (FR), STMicroelectronics (Switzerland) (CH), Aix-Marseille Université (FR), STMicroelectronics (United States) (US)
Association Nationale de la Recherche et de la Technologie
Affordable and clean energy
Openalex Percentile: Top 90%
VLSI and Analog Circuit Testing
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