HDL Implementation of feedforward neural network (FNN)

Abstract Feedforward neural network (FNN) based classifiers have been widely applied to classification tasks such as speech and image recognition. FNN classifier’s computations require matrix-vector multiplications; hardware implementations of the classifier are a good option for achieving better performance. However, embedding a large number of parameters of an FNN classifier onto hardware becomes a difficult choice. The present work demonstrates Verilog hardware description language (HDL) implementation of the FNN with Cadence NCSIM and synthesizes with GENUS tool at CMOS 180 nm, 90 nm, and 45 nm technology nodes with process corner variation. The choice of technology node and corner becomes crucial in determining the power efficiency and performance of the network. The choice of process corner significantly impacts power and delay characteristics in artificial neural network (ANN) circuits; smaller technology nodes offer higher transistor density and potentially better performance, but come at the cost of power consumption. At the technology node of CMOS 45 nm, power consumption drops by over 95% from 237.1 μW to 13.12 μW when shifting from the fast to slow corner, while delay increases by 24% from 2.255 ns to 2.802 ns. The present work would be a helpful resource for the designer to select the technology node and process corner based on performance metric constraints.