Evaluation of ESF3 Split-Gate Cell Cycling Endurance for Eeprom Applications

An extended Program/Erase cycling endurance study was performed on SuperFlash ESF3 split-gate cells to evaluate the feasibility of its usage in byte-erasable EEPROM architecture. It was shown that by using optimized program and erase conditions with ramped pulses it is possible to significantly reduce the degradation of erase speed compared to a single-pulse cycling, and to obtain cell endurance exceeding one million cycles. Use of error correction can further increase the array endurance capability with about 7 million cycle endurance predicted at 6 sigma level for optimized program/erase conditions.