An Oscillator-Free LO Generator for Beyond 5G Wireless Communication Systems

This study presents a new synthesizer cascade topology of a delay-locked loop (DLL) and a programmable frequency multiplier (PFM) for 5G<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> communication systems. The proposed synthesizer comprises an intermediate frequency (IF) synthesizer and an RF PFM. The unique IF synthesis through a 512-phase DLL and a 512-to-1 multiplexer provides the output frequency range of 156.25–357.14 MHz when the reference clock frequency, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{\mathrm {ref}}$</tex-math> </inline-formula>, is 156.25 MHz, which is up-converted to, radio frequency, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{\mathrm {rf}}$</tex-math> </inline-formula>, range of 1.25–5 GHz by the PFM. The corresponding channel resolution range is approximately 4.9–45.05 MHz. Consequently, the proposed synthesizer provides a wide 120% output frequency bandwidth and a finer channel resolution than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{\mathrm {ref}}$</tex-math> </inline-formula>. The presented synthesizer is fabricated in a 65-nm CMOS process, and its active die size is 0.68 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The total power consumption is 17.7 mW, and the integrated rms jitter from 1 kHz to 100 MHz of 5 GHz is measured as 32 fs.