High-Performance Digital Circuit Architectures for Accelerated Number Theoretic Transform Computation

This research paper aims to improve the applications that need fast polynomial multiplication, particularly errors-correcting codes and encryption, where the Number Theoretic Transform (NTT) is an essential tool. High-performance digital circuit topologies that accelerate modular arithmetic operations, including modular multiplication, subtraction, and addition, are proposed in this work to increase the efficiency of NTT computation. The architecture uses parallel processing and pipeline techniques to greatly increase performance. The implementation of optimization techniques can also be part of the resource-sharing systems, bit-reversal elimination, and efficient butterfly unit design, which also reduces latency and area overhead. The recommended design is developed and evaluated using a digital simulation framework, yielding a significant improvement in throughput and energy efficiency compared to existing systems. The experiments that demonstrate the design are scaled for input sizes and are appropriate for real-time cryptography systems. This work replicates the groundwork for the usage of NTT computation in the future with safe and efficient computing systems by moving into how algorithmic developments and hardware optimizations can be work together to provide high-speed NTT computation.