An Electrode Design Strategy to Minimize Ferroelectric Imprint Effect

The phenomenon of ferroelectric imprint, characterized by an asymmetric polarization switching behavior, poses significant challenges in the reliability and performance of ultra-low-voltage ferroelectric devices, including MagnetoElectric Spin-Orbit devices, Ferroelectric Random-Access Memory, Ferroelectric Field-Effect Transistors, and Ferroelectric Tunnel Junctions. In this study, the influence of electrode configuration in different device architectures are systematically investigated on their imprint effect. By tuning the work function of La_0.7Sr_0.3MnO₃ (LSMO) electrodes through oxygen pressure during deposition, precise control over the built-in voltage offset (V_offset) in ferroelectric capacitors are demonstrated. This results reveal that higher oxygen pressures increase the work function of LSMO, effectively compensating for V_offset and enhancing device stability. Finally, a ferroelectric device with a hybrid bottom electrode of LSMO and SrRuO₃ is optimized to mitigate the imprint effect. The optimal device showcases small coercive voltage of 0.3 V, a minimal V_offset of 0.06 V, excellent endurance (electrical cycle up to 10⁹), and robust zero bias applied polarization retention. These findings provide a practical guideline for electrode design in ferroelectric devices, addressing the imprint effect and improving operational reliability. This approach, combining material tuning and in situ diagnostics, offers a pathway to optimize ferroelectric device performance, with implications for advancing ultra-low-power electronics.