LHCA: a new low-power, high-speed carry skip adder using hybrid memristor-MOS logic

Abstract In this paper, the authors represent a new low-power, high-speed carry-skip adder using hybrid memristor-MOS logic (LHCA). The proposed LHCA uses the memristor ratioed logic (MRL) technique, which is compatible with traditional CMOS technology and suitable from a fabrication point of view. The proposed LHCA is theoretically analyzed and simulated using LTSpice software using 45 nm CMOS technology with supply voltages of 1 V. The performance of the proposed LHCA is analyzed and compared with the existing CMOS-based design. The results show that the proposed LHCA design performances are improved compared to the state-of-the-art design by approximately 22.9% smaller delay, consuming only 82% of the power, and 86.1% reduction in power-delay-product (PDP). Moreover, the total component count is 114 (38 MOSFETs and 76 Memristors) compared to the state-of-the-art design requiring 184 MOSFETs. This shows that the proposed design occupies a smaller area. The proposed LHCA is suitable for high-speed, low-power, high-density, and battery-operated handheld applications.