Highly‐Effective Thermoelectric Cooling for Power Semiconductor Devices Packed with Thermal‐Expansion Offset and Flame Retardancy Epoxy Resin

Abstract The high‐power‐density and high‐temperature operation of third‐generation power semiconductor devices (e.g., SiC/GaN) is limited by epoxy resin (EP)‐based packaging materials due to three key challenges: (1) Low thermal conductivity brings heat accumulation; (2) High interfacial stress from the ≈ 20 times higher thermal expansion coefficient of EP versus SiC/GaN causes thermal cycling‐induced interfacecracks, significant performance or lifespan degradation and even device failure; (3) The flammable nature of EP enhances the risk factor caused by thermal runaway. Herein, a thermal‐expansion offset and flame retardant Zn 1.5 Cu 0.5 P 2 O 7 (ZCPO) is design with a negative thermal expansion coefficient of ‐20 × 10 −6 / °C, within temperature ranges of 20 ∼ 190 °C, which enables to achieve a ceramic‐like thermal expansion coefficient (4 × 10 −6 / °C) and UL‐94 V‐0 rating flame retardancy in ZCPO/EP‐61 composite for the first time. The perfectly matched thermal expansion coefficient minimizes the interfacial stress between EP and chips or thermoelectric cooler, thus a simple thermoelectric cooling architecture is designed for power semiconductor device without thermal interface material 2 (TIM2), which enables to achieve a cooling temperature of 26.85 °C, 8 °C lower than that with TIM2 (18.89 °C).