Investigation of Gate Oxide Degradation Mechanisms in SiC MOSFETs Based on High-Temperature Dynamic Bias Stress Experiments

This paper systematically investigates the failure mechanisms of gate oxides in silicon carbide (SiC) MOSFETs, aiming to enhance gate reliability. Through long-term high-temperature dynamic bias (HTDB) stress experiments on 4H-SiC MOSFETs, the degradation behavior of gate oxides under various stress conditions is revealed. The study demonstrates that the energy-level-dependent distribution of interface state density (Dit) significantly impacts device performance. By optimizing nitric oxide (NO) post-oxidation annealing processes, the threshold voltage (Vth) drift and capacitance-voltage (C-V) hysteresis are effectively reduced by 35% and 22%, respectively. Furthermore, a novel interface state characterization method combining high-low frequency C-V measurements is proposed, providing enhanced accuracy in evaluating gate oxide quality under bias stress. These findings offer critical theoretical insights and process optimization strategies for improving SiC MOSFET reliability in extreme environments (elevated temperatures >200C, high-frequency operations >100 kHz), thereby accelerating the commercialization of SiC power devices.