Enhanced POSIT Constant Multiplier Implementation using FPGA

Field-programmable gate arrays (FPGAs) are becoming increasing attractive in hardware designs due to their high performance, power efficiency, and reconfigurable nature. However, multiplication is one of the most area and power hungry operations on FPGAs. To address these issues, we propose an enhanced constant multiplier (ECM) in the POSIT format for performance, area and energy efficiency. POSIT is a promising alternative numbering system with its unique dynamic bit allocation to the traditional IEEE-754 floating-point numbering system. The proposed ECM was implemented using Verilog on an Artix 7-series FPGA device. The ECM utilizes a unique type of power-efficient leading one detector (LOD), with cleverly mapping the multipliers in the Digital Signal Processor (DSP) units to perform the constant multiplication process. Compared to traditional POSIT constant multipliers, the ECM demonstrates substantial improvements: a 32% reduction in area, a 34% reduction in delay, a 28% reduction in power consumption, and a 53% reduction in energy, all without sacrificing accuracy.