Signal Integrity Enhancement of Die-to-Die Interconnection by Using a Vertically Asymmetric Pattern

Enhancing signal integrity (SI) in high-speed die-to-die interconnections is crucial to ensure stable and reliable system performance. Interconnection structures influence insertion loss (IL) and crosstalk performance, and the structural optimization is essential in improving SI. To address these challenges, this study proposes a vertically asymmetric pattern for die-to-die interconnections. The proposed design repositions the traces to mitigate SI degradation. Frequency domain analysis using Ansys HFSS demonstrates a significant improvement in IL, meanwhile time domain analysis shows a 36. 8% improvement in the worst-case eye diagram Rx mask width. These findings validate the effectiveness of the proposed design in improving SI and advancing the development of high-speed die-to-die interconnections.

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Publication Details

Published
2025-04-15
DOI
https://doi.org/10.23919/icep-iaac64884.2025.11002962
Citations
1
Primary Topic
Integrated Circuits and Semiconductor Failure Analysis
Type
article
Field-Weighted Citation Impact
0.73
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article

Signal Integrity Enhancement of Die-to-Die Interconnection by Using a Vertically Asymmetric Pattern

Kihun Ok, Jaewon Lee, SoYoung Kim
1 citations
Integrated Circuits and Semiconductor Failure Analysis
0.73
article

Signal Integrity Enhancement of Die-to-Die Interconnection by Using a Vertically Asymmetric Pattern

Kihun Ok, Jaewon Lee, SoYoung Kim
article en
1 citations

Abstract

Enhancing signal integrity (SI) in high-speed die-to-die interconnections is crucial to ensure stable and reliable system performance. Interconnection structures influence insertion loss (IL) and crosstalk performance, and the structural optimization is essential in improving SI. To address these challenges, this study proposes a vertically asymmetric pattern for die-to-die interconnections. The proposed design repositions the traces to mitigate SI degradation. Frequency domain analysis using Ansys HFSS demonstrates a significant improvement in IL, meanwhile time domain analysis shows a 36. 8% improvement in the worst-case eye diagram Rx mask width. These findings validate the effectiveness of the proposed design in improving SI and advancing the development of high-speed die-to-die interconnections.

Sungkyunkwan University (KR)
Openalex Percentile: Top 28%
Integrated Circuits and Semiconductor Failure Analysis
0.73
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Signal Integrity Enhancement of Die-to-Die Interconnection by Using a Vertically Asymmetric Pattern — Kihun Ok, Jaewon Lee, et al. · (2025) | TGRS Research Map | TGRS