Elemental Characterization for Electroless Cu Interface Layer of Stacked Micro-via in Substrate by STEM and ToF-SIMS
We investigated the electroless Cu interface layer of stacked micro-via in the substrate, prepared by two methods; a Ni-added electroless Cu plating and a Ni-free (OPC-FLET) one. We found nanovoids existed in the electroless Cu interface layer in an as-made state and grew or occurred during the thermal cycle test. Hydrogen concentration is less in the Ni-free electroless Cu layer, which means the OPC-FLET process is less susceptible to hydrogen embrittlement.
Authors
- Yuhei Kitahara
- Hiroyoshi Yoshida
- Kei Hashizume
- Aiji Suetake
- Masahiko Nishijima (ORCID: https://orcid.org/0000-0002-5143-7558)
- Katsuaki Suganuma (ORCID: https://orcid.org/0000-0003-2137-9905)
- Chuantong Chen
- Rieko Okumuara
- Zheng Zhang (ORCID: https://orcid.org/0000-0002-1490-6394)
- Kimihiro Yamanaka
- Ming-Chun Hsieh
- Hiroki Seto
Institutions
- The University of Osaka (JP)
Publication Details
- Published
- 2025-04-15
- DOI
- https://doi.org/10.23919/icep-iaac64884.2025.11003015
- Primary Topic
- 3D IC and TSV technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.00