High-Performance Implementation Architecture for Additive Homomorphic Encryption Algorithms on FPGA

Additive homomorphic encryption is one of the key technologies for ensure data privacy in federated learning. To accelerate these algorithms, several studies have deployed homomorphic encryption algorithms on parallel platforms, such as FPGAs. Although many works have demonstrated good acceleration effects, an efficient and generalizable implementation architecture remains lacking. In this paper, we propose an efficient FPGA implementation architecture compatible with various partially homomorphic encryption algorithms. First, an efficient modular multiplier which supports dynamic modulus length is designed. We introduce the redundant number system and design an iteration cycle control module to reduce computing cost and to fit the modulus with different length, respectively. Secondly, a high-performance FPGA implementation architecture compatible with multiple additive homomorphic encryption algorithms is proposed. Based on the processes of algorithms, we propose a customized multifunctional multiplier and a top-level control module to realize a full reuse without any performance loss. According to implementation results on Kintex UltraScale XCKU060, the encrypt speed of Paillier and OU achieves 473.79 OP/s and 88.96 OP/s under 128-bit security, respectively. Compared with existing similar works, our architecture achieves 8.4 × speedup, demonstrating its performance and functional advantages.