Linearity Calibration Method for Stochastic Time-to-Digital Converters

Stochastic Time-to-Digital Converters (STDCs) can theoretically achieve very fine time resolutions utilizing random time offsets caused by device mismatch rather than relying on delay elements. However, the random time offsets follow a Gaussian distribution, which result in non-ideal TDC output characteristics, such as irregular gain and nonlinearity that may severely degrade the conversion performance. Until now, there have been few previous studies on the linearity calibration of STDCs because the STDCs employ a large number of arbiters and calibrating the individual arbiters may require significant time and effort. In this paper, we propose a linearity calibration algorithm called Arbiter Selection for Maximum Linearity (ASML) that efficiently yet effectively calibrates STDCs. To verify the effectiveness of the algorithm, we performed high-level simulations in MATLAB based on measured circuit parameters from an STDC chip fabricated in a 65nm CMOS process, assuming a 6-bit STDC with 2-bit redundancy. Further, we explore the benefits of the proposed ASML algorithm for higher bit resolution STDCs. The simulation results show the proposed algorithm can be beneficial, especially at high bit resolutions. For a 9-bit STDC with 2-bit redundancy, the proposed algorithm achieved more than 11 times better linearity compared to the conventional bit truncation method.