Low-Loss Integration Strategy for Regularly Spaced ICs in Unconventional Phased Arrays Beyond 100 GHz

This study investigates the design and synthesis of tiled planar phased arrays operating beyond 100 GHz, focusing on the impact of insertion losses between regularly placed integrated circuit (IC) ports and tiles. To address the interconnect challenge, the problem is simplified to a two-dimensional framework and formulate a novel multi-objective optimization problem aimed at minimizing insertion losses while ensuring optimal array performance across fully digital and hybrid/analog systems. The proposed framework has been successfully applied to tetromino-based <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\lambda_{0}$</tex> /2-spaced clustered 8×8 planar arrays, consisting of sixteen subarrays at 135 GHz. These arrays were integrated with four ICs, each equipped with four output ports. In particular, Manhattan and Euclidean routing techniques are applied for the optimized irregular array configuration resulting in 2.7 dB and 2.5 dB insertion losses between IC ports and tiles on average, respectively. The effectiveness of the proposed approach has been validated through numerical full-wave simulations.