Advanced Post Overlay Compensation for Enhanced Lithography Overlay Accuracy for Next-Generation AICS Packaging

Advanced IC substrates (AICS) must accommodate larger packaging areas, higher I/O density, smaller ball pitches, and more packaging layers for next generation device demand. Achieving these goals requires lithography with extremely large exposure fields and fine resolution. Large exposure fields enable stitching-free exposure over large areas, while fine resolution supports tighter line/space dimensions and finer ball pitches for higher I/O density. However, the increasing number of layers and finer RDL pitches introduce significant challenges, particularly tight overlay budgets. Alignment errors are a major source of overlay inaccuracies and hinder yield and precision. To address this, we propose advanced post overlay compensation technology. This method leverages algorithms to analyze correctable overlay components and applies real-time corrections during lithography, significantly improving overlay accuracy and yield.