Design of a Digital Full Adder Circuit in 16 nm FinFET Process

Digital full adders are one of the major basic building blocks of modern high-performance arithmetic logic units due to which a wide range of full adder cells have been designed over the course of this. This research presents the design of a 1-bit full adder circuit in 16 nm FinFET process. Rather than using conventional CMOS logic, a hybrid logic style has been utilized. At first, a simultaneous XOR-XNOR signal generation circuit has been designed. Later, this XOR-XNOR circuit has been utilized as an input to sum and carry generation circuits. While simulating in 16 nm FinFET process with 0.8 V as supply, the design has a power dissipation of 1.29 μW and a worst-case delay of 12.23 ps. Also, performance analysis with different supply voltages has been conducted. The design presented in this research obtained better performance compared to the single logic Mirror CMOS full adder and several other state-of-the-art hybrid logic style based full adders.