RDL Formation Using Low Df Thermosetting Film: Progress of the Chiplet Integration Platform Consortium in Japan
As AI applications demand greater computing power, limitations of traditional semiconductor IC technology have become significant, making chiplet integration a promising solution. One of the themes of “the Chiplet Integration Platform Consortium” in Japan is to develop chiplet integration technology using bridge architecture. The “Pillar Suspended Bridge (PSB)” was devised by the Consortium to achieve the simplest possible chiplet integration structure. We developed proof-of-concept (PoC) of the polymer redistribution layer (RDL) bridge with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{\Phi 2}\boldsymbol{\mu}\mathbf{m}$</tex> vias, applied low dissipation factor (Df) thermosetting film with favorable properties.
Authors
- Yasuhiro Morikawa
- Takafumi Fukushima (ORCID: https://orcid.org/0000-0003-2303-8178)
- Ichiro Kono
- Yoshifumi Naka (ORCID: https://orcid.org/0000-0003-1808-7063)
- Meiten Koh
- Yoichiro Kurita
Institutions
- Tohoku University (JP)
- Institute for Future Engineering (JP)
- Institute of Science Tokyo (JP)
Publication Details
- Published
- 2025-04-15
- DOI
- https://doi.org/10.23919/icep-iaac64884.2025.11003034
- Primary Topic
- 3D IC and TSV technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.00