Analysis of Parasitic Effects in Packaging with RDL

The purpose of this study is to effectively simulate and optimize the design of this power module packaging architecture, effectively reducing the direct current resistance (DCR) effect. Due to the high power output accompanied by significant heat dissipation, the unavoidable factor is the direct current resistance effect on the circuit. Additionally, during circuit operation, unnecessary parasitic inductance and capacitance are generated between components and circuits, which can cause electromagnetic interference (EMI) and increase switching losses in the overall system. Therefore, this project simulates and analyzes the resistance and parasitic inductance from power to ground in the VQFN (very-thin quad flat no-lead) package with Power module chips using the RDL process. By optimizing the structural design, the Via size, spacing, and quantity are improved to obtain the optimal structure and results.