Development of Warpage Control Techniques in Multi-Chip Fan-Out System-in Package (SiP) Using Redistribution Layer Technology

The study focuses on the control and optimization of warpage in multi-chip fan-out system-in-package (SiP) technology, examining the effects of epoxy molding compounds (EMCs) and the die/reticle area ratio on packaging performance. Through experimental design, the optimal EMC material and area ratio were identified and successfully implemented in actual packaging processes. The results indicate that selecting EMC2 and increasing the die/reticle area ratio to 55% significantly reduce warpage. After multiple reflow cycles, the warpage of the multi-chip SiP modules was only 136 µm, meeting JEIT A standards. Furthermore, cross-sectional analysis and bonding tests demonstrated that this packaging design effectively prevents delamination between the molding material and redistribution layers (RDL) or dies, while ensuring high-quality bonding between Cu pillar bumps and pads.