Cu Pilliar Plating Process on Lare Panel Fan-Out for High Performance Computing Application

AI and HPC (High-speed computing) chips require copper pillar structures to meet the requirements of low noise and reduced energy consumption. The electroplating copper pillar process has technical difficulties in terms of uniformity. If we want to further use large-size panel-level packaging technology to be production platforms, that is even more challenging. This article proposes to enable large-size panel-level electroplating copper pillar process to have mass production capabilities through the machines and design of special structures.