VLSI design of symmetric two-dimensional finite impulse response filter architecture using approximate circuits and parallel Processing

• The symmetry in the 2-D filter coefficients reduces the number of multipliers required for the architecture. In this proposed work, diagonal symmetry filter architecture is realized for the filter length N = 8. • Block processing is introduced in the filter structures to increase the throughput of the overall architecture and to reuse the memory. • The remaining multipliers of symmetry filter architecture are realized by the proposed approximate low power tree multipliers instead of traditional power complex multipliers. • The symmetry filter design is explored along with the General Filter (GF) by considering filter lengths of N = 8 and L = 2 using proposed multipliers,. • The designs are represented by Verilog HDL and synthesized in reconfigurable FPGA and ASIC-custom design tools. • The area, power, and delay reports are generated for comparative analysis with the state-of-the-art 2-D FIR Filter architectures. This study presents an innovative filter architecture for a Two-Dimensional (2-D) FIR filter and illustrates its implementation in VLSI design through symmetric processing, parallelism, and approximate computing principles. When L is the block size, the architecture incorporates parallel processing to augment throughput by a factor of L. Symmetry is incorporated into the filter coefficients to minimize the number of multipliers needed for filter design. Approximate multipliers have been employed instead of the exact multipliers to reduce size and power usage. The diagonal symmetry coefficient matrix is analyzed, and consequently, the filter design is explored and implemented utilizing the proposed approximation multiplication technique with innovative approximate adders and compressors. The suggested filter design demonstrates minimum resource requirements in terms of hardware components and computational power. The hardware utilization summary is assessed for the architecture in Verilog HDL and its subsequent synthesis by Xilinx tools for the FPGA target device. Area, delay, and power reports are produced using Cadence's Genus tools for ASIC design in 45 nm CMOS technology. The examination of contemporary 2-D FIR filter designs versus traditional multiplier-based filter architectures emphasizes area, delay, and power consumption measurements. The suggested work plan is presented, detailing the Innovus technologies employed for placement and routing determination. The area, power, and delay reduction attained by the recommended symmetry filter is 51.9 %, 36.5 %, and 32.17 % than the general filter using normal multipliers and un-symmetry. The ADP & PDP of the suggested filter structure is decreased by a minimum of 73.5 % & 27.19 % and a maximum of 98.66 % & 96.86 % compared to the current filter topologies. Additionally, real-time FPGA testing on the Xilinx Zynq-7000 platform validated the proposed 2-D FIR filter design, demonstrating high throughput and efficiency for edge vision applications.