A High-Speed Low-voltage Low-power CMOS Dynamic Comparator

High-speed and low-voltage comparators are considered basic building blocks for analogue-to-digital converters. This paper presents a dynamic two-stage comparator that significantly improves the performance of existing designs in the literature, particularly in terms of speed and power consumption. The comparator features a modified preamplifier stage with two interconnected control transistors, which improve its performance by reducing delay and increasing speed. Simulations using the Cadence tool in a 90 nm CMOS process show a delay of 257 ps and a power consumption of just 16.8 nW at a supply voltage of 0.75 V, highlighting its robustness compared with conventional comparators.