A 2× Time-Interleaved 4-GS/s 14-Bit DAC With On-Chip Calibration of Interleaving Nonlinearities

This work presents a high-linearity 2× time-interleaved (TI) current-steering (CS) digital-to-analog converter (DAC) facilitated by an on-chip calibration approach. In order to accurately analyze the impact of interleaving errors on high-resolution TI-DAC, a comprehensive function of spurious-free dynamic range (SFDR) is derived from time-domain modeling. Based on theoretical analysis, a foreground two-step calibration scheme with low-complexity circuits is proposed to address the issue of SFDR degeneration caused by narrowband locking. The calibration of gain error mismatch (GEM) can be achieved by efficiently compensating for the current sources of each sub-DAC (sDAC) in the proposed GEM loop. The amplitude of the TI spurs induced by duty-cycle errors (DCEs) exhibits an unimodal linear characteristic. Based on this characteristic, a compact cyclic-quantization circuit (CQC) combined with a uniform grid search algorithm is proposed to realize a high-precision calibration for DCE. A 14-bit 4-GS/s TI-DAC with the foreground on-chip calibration is realized in 65-nm CMOS. Measurement results demonstrate that with one single-tone calibration, the SFDR can be improved up to around 25 dB, achieving an SFDR <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\ge$</tex-math></inline-formula> 61 dB across the entire first Nyquist zone.