A 1998-Mpixels/s 75-pJ/pixel Slice-Alternated Display Stream Compression Encoder

Display Stream Compression (DSC) standard pro-vides visually lossless video quality while maintaining low latency and low cost. In this paper, an efficient DSC encoder architecture is proposed, which supports 1, 2, and 4 slices per line, based on three novel techniques: 1) slice-alternated architecture, which reuses on-chip memory and computing resources across multiple slices; 2) unbalanced prediction loop pipeline address timing constraints caused by dependencies among prediction pi, and achieve a throughput of 3 pi/cycle; 3) default update and spe-cial group adjustment are proposed in inde× color history (ICH) to achieve minimal delay and higher throughput. Implemented in TSMC 28nm CMOS technology, the proposed DSC encoder oc-cupies a core area of 0.6 mm2 with 440K logic gates and 36.8 KB of SRAM. Operating at 333 MHz, it delivers a throughput of 1998 Mpi/s, enabling real-time processing of 4K UHD resolu-tion. It also demonstrates earea efficiency, achieving a throughput-to-area ratio of 3330 Mpps/mm2. Furthermore, it maintains a power consumption of 150 mW (75 pJ/pi). Com-pared to the state-of-the-art studies, this design achieves im-provements of up to 1.4×, 2×, and 1.2× in throughput, area effi-ciency, and energy consumption respectively.