A 21.6-bit Programmable-Gain Triple-Sampling Incremental ΔΣ ADC With 4 ppm INL for Bridge Transducers

This article presents a high-resolution programmable-gain incremental delta-sigma (ΔΣ) analog-to-digital converter (ADC) optimized for high-accuracy bridge transducer measurements. The proposed design incorporates a triple-sampling (TRS) technique and an auto-zeroing (AZ) integrator that are effectively combined to suppress DC offset and 1/<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> noise, reduce input-referred noise (IRN), and improve effective resolution (ER). Implemented using a switched-capacitor (SC) ΔΣ modulator architecture, the proposed ADC provides accurate gain control without the need for additional power-hungry amplifiers. With the AZ-TRS integrator, a low IRN of 1.03 μV<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RMS</sub> is achieved. Furthermore, the ADC demonstrates an integral nonlinearity (INL) of ±4 ppm across all gain settings, with a maximum gain of 13. Additionally, it achieves power supply rejection ratio (PSRR) and common-mode rejection ratio (CMRR) values of 117.1 dB and 122.0 dB, respectively. The prototype chip was fabricated using a 0.18-μm CMOS process, and the ΔΣ modulator occupies a compact area of 0.34 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The ADC operates with a supply voltage of 3.0 V and a current consumption of 361 μA for the analog circuitry, while the digital filter consumes 36 μA at 1.8 V.