Cache-PIM: An ECC-Compatible eDRAM Processing-in-Memory for Last-Level Cache With Triple-Level Error Correction

This article presents cache-processing-in-memory (PIM), an error correction code (ECC)-compatible embedded dynamic random access memory (eDRAM) PIM-based last-level cache (LLC) with a novel triple-level error correction. Integrating PIM into the cache system causes the existing ECC to become a performance bottleneck, leading to higher latency and decreased computational accuracy. An ECC-compatible eDRAM-PIM enables reliable in-memory computing (IMC) even in less stable DRAM environments while reducing ECC latency for PIM tasks. Cache-PIM proposes three key features: 1) triggered error correction with concurrent error detection (TECCED) reduces cell error correction latency for PIM tasks; 2) adaptive error canceling (AEC) corrects computation errors; and 3) resolution-aware single-cycle voting (RSV) reduces analog-to-digital converter (ADC) readout error. Cache-PIM is fabricated in 28-nm CMOS technology and occupies 0.66-mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die area. A demonstration of ViT-Base on the ImageNet dataset achieves 61% latency reduction compared to the conventional ECC and 77.1% accuracy.