A Low-Power Low-Voltage Binary Search Analog-to-Digital Converter

This paper introduces an enhanced design for a low-voltage, low-power, 3-bit binary-search analog-to-digital converter (ADC), focusing on optimizing the performance of the comparator used in fast ADC circuits. The proposed solution features a modified dual-tail comparator, designed for lower technology nodes and reduced supply voltage, improving overall efficiency. Unlike traditional architectures that require 2<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</sup>-1 comparators, the new design reduces the number of comparators needed, 2N-1, achieving better resource utilization. The system includes a sample-and-hold circuit, an encoder, a D-latch, five voltage comparators, and two logic gates. Simulation results using Cadence with 90 nm CMOS technology at a supply voltage of 0.75 V reveal exceptional efficiency, with a power consumption of just 39.9 µW and a bandwidth of 1.11 GHz, making it suitable for next-generation high-performance, low-power ADC applications.