Design of GaN-based Phase-Locked Dielectric Resonator Oscillator for Strategic Applications

Electronic warfare systems have stringent requirements of ultra-low phase noise and substantial high power oscillators thus demanding an additional amplifier to drive subsequent stages. Most of the oscillator designs realized using GaAs/SiGe technology has the advantage of low phase noise profile but offer low output power. GaN-based Dielectric Resonator Oscillators (DRO) could be one of the solutions, in terms of high power, quality factor, and compact size. The phase noise profile can be further improved by Phase Locking loops (PLL). In this work, a hybrid phase-locking technique that amalgamates the salient features of the two most common techniques available in the literature - viz., Analog PLL and Digital PLL, is presented. This design of state-of-the-art GaN-based PL-DRO presents a substantial output power of 24 dBm at 12 GHz with excellent phase noise of -119 dBc/Hz at 100 kHz offset frequency. Performance evaluation has been carried out comparing with the state-of-the-art published literature. The suggested phase-locking approach can be used to design ultra-low phase noise DROs for strategic electronics communication systems.