An FPGA SoC-based radiation-hardened design for multibit upset mitigation

In space and high-radiation environments, electronic systems based on SRAM-type FPGAs are susceptible to single-bit upsets (SBUs) and multi-bit upsets (MBUs) caused by high-energy particle strikes, which can affect the FPGA's logic functionality and system performance. Although Triple Modular Redundancy (TMR) technology can effectively enhance fault tolerance, it results in significant resource overhead, especially in SoC systems where on-chip memory resources in FPGAs are used as caches. This paper proposes a radiation-hardened system that combines TMR with Single Error Correction, Double Adjacent Error Correction, and Triple Adjacent Error Correction (SEC-DAEC-TAEC) coding. The system employs TMR for the processor design, while on-chip caches are hardened using SEC-DAEC-TAEC coding. Experimental results demonstrate that this system ensures reliability while significantly reducing the usage of FPGA onchip memory resources, and showing substantial engineering significance.