A 50-kHz BW 92.1-dB SNDR Incremental ADC Using a Back-End Sampling Two-Step NS-SAR Architecture with Concurrent Gain-Error + Noise Suppression

Emerging wearable/implantable healthcare electronics and distributed AI edge sensors desire high-resolution ADCs with low power consumption and relaxed signal-chain overhead (e.g. input drivers and reference buffers). SAR and Incremental <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta\Sigma$</tex> modulator (IDSM) are commonly chosen architectures for their superior efficiency and low-latency multiplexable conversion; but many existing designs impose a significant signal chain burden, primarily due to the kT/C noise suppression requirements and the need for a large oversampling ratio, compromising the system efficiency. While techniques such as sub-ranging [1], detect-and-skip [2], zoom [3], background-tracking [4], and extended-counting [5] can be mixed-and-matched to alleviate reference buffer burden and oversampling ratio, input driving relaxation still remains challenging under the constraints of kT/C noise and linearity. Recently, Wang et al. [6] presented a noise-shaping (NS) SAR based IADC that incorporates digital prediction and kT/C cancellation achieving >90dB SNDR with 0.8-pF C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IN</inf>; however, the architecture loses the multiplexing capability and is sensitive to amplifier gain variation. Another work by Li et al. [7] proposed a driver embedded two-step SAR ADC combining analog prediction and flipped voltage follower (FVF) to provide linear internal buffering. Nonetheless, this technique requires a power-hungry, PVT-sensitive OTA-based predictor, while the FVF contributes extra noise during the SAR conversion, resulting in limited efficiency improvement.