A 17.4fJ/conv.-step, 202µm<sup>2</sup>, 1.5GS/s and PVT-Tolerant 7-Bit Charge-Injection SAR ADC in 28nm CMOS Using a Background-Calibrated 1-Bit Metastability Detector and a gm-Boosted StrongARM Comparator

Charge-injection successive approximation register (CI-SAR) ADC has emerged as an alternative area-efficient ADC architecture for medium-resolution >GS/s high-speed ADCs [1]–[4]. By replacing the area-hungry multi-bit capacitor digital-to-analog converter (CDAC) [5]–[7] with the transistor-based charge-injection DAC (CI-DAC), CI-SAR has demonstrated substantially higher area efficiency than conventional CDAC-based SAR ADC in terms of GS/s/µm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. This attractive feature, however, comes at the cost of performance susceptibility to voltage and temperature variation. Specifically, the full scale of the CI-DAC depends heavily on the amount of average charge transferred during the bit cycling. The top-left of Fig. 1 (challenge #1) shows the simulated SNDR of the conventional CI-SAR, which suffers severely at low temperature and at high supply voltage due to full-scale variation. Also, just like a conventional SAR ADC, the CI-SAR faces a tight tradeoff between power and conversion speed (challenge #2). For instance, the common-mode of the CI-DAC output monotonically decreases over bit-cycling, and this necessitates a comparator topology whose resolving time is invariant to the input common-mode. While the double-tailor triple-tail comparator can be used, prior research in [5] revealed that the double-tail topology consumes more power than the strongARM comparator for comparable noise performance. Lastly, extracting additional bits from the metastability of the comparator in ADC has been demonstrated in previous works [1], [8], [9], [10], but it is tricky to use as it is highly subject to PVT variation (challenge #3). Therefore, auxiliary circuitries supported by complex calibrations are often required to correctly set the threshold of metastability detectors [8].

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Published
2025-04-13
DOI
https://doi.org/10.1109/cicc63670.2025.10983098
Citations
1
Primary Topic
CCD and CMOS Imaging Sensors
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article
Field-Weighted Citation Impact
0.73
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article

A 17.4fJ/conv.-step, 202µm2, 1.5GS/s and PVT-Tolerant 7-Bit Charge-Injection SAR ADC in 28nm CMOS Using a Background-Calibrated 1-Bit Metastability Detector and a gm-Boosted StrongARM Comparator

Chaeeun Lee, Jong-Ho Kim, Jintae Kim
1 citations
CCD and CMOS Imaging Sensors
0.73
article

A 17.4fJ/conv.-step, 202µm2, 1.5GS/s and PVT-Tolerant 7-Bit Charge-Injection SAR ADC in 28nm CMOS Using a Background-Calibrated 1-Bit Metastability Detector and a gm-Boosted StrongARM Comparator

Chaeeun Lee, Jong-Ho Kim, Jintae Kim
article en
1 citations

Abstract

Charge-injection successive approximation register (CI-SAR) ADC has emerged as an alternative area-efficient ADC architecture for medium-resolution >GS/s high-speed ADCs [1]–[4]. By replacing the area-hungry multi-bit capacitor digital-to-analog converter (CDAC) [5]–[7] with the transistor-based charge-injection DAC (CI-DAC), CI-SAR has demonstrated substantially higher area efficiency than conventional CDAC-based SAR ADC in terms of GS/s/µm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. This attractive feature, however, comes at the cost of performance susceptibility to voltage and temperature variation. Specifically, the full scale of the CI-DAC depends heavily on the amount of average charge transferred during the bit cycling. The top-left of Fig. 1 (challenge #1) shows the simulated SNDR of the conventional CI-SAR, which suffers severely at low temperature and at high supply voltage due to full-scale variation. Also, just like a conventional SAR ADC, the CI-SAR faces a tight tradeoff between power and conversion speed (challenge #2). For instance, the common-mode of the CI-DAC output monotonically decreases over bit-cycling, and this necessitates a comparator topology whose resolving time is invariant to the input common-mode. While the double-tailor triple-tail comparator can be used, prior research in [5] revealed that the double-tail topology consumes more power than the strongARM comparator for comparable noise performance. Lastly, extracting additional bits from the metastability of the comparator in ADC has been demonstrated in previous works [1], [8], [9], [10], but it is tricky to use as it is highly subject to PVT variation (challenge #3). Therefore, auxiliary circuitries supported by complex calibrations are often required to correctly set the threshold of metastability detectors [8].

Konkuk University (KR)
Affordable and clean energy
Openalex Percentile: Top 28%
CCD and CMOS Imaging Sensors
0.73
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