An 18-Bit 183.9dB-FoM_S,DR MES/Calibration-Free Scalable Zoom ADC Using Fully Passive Coarse Modulator and Gain-Linearity-Enhanced FIA with Sub-1ppm-THD at Full Scale Input in 65-nm CMOS

High-resolution (SNDR>100dB) and high energy efficiency (FoM>180dB) ADCs can be applied to many applications such as Internet-of-Things (IoT) smart sensors and wearable biopotential signal acquisition systems. Moreover, in fields such as high-fidelity audio and precision instrumentation, ADCs are also required to exhibit high linearity, typically with a THD of below -120dB. Zoom ADC is a kind of emerging hybrid architecture ADC that combines low-power SAR ADCs and low-distortion ΔΣ ADCs, achieving high energy efficiency and linearity through coarse and fine two-step conversions [1]–[7]. However, traditional zoom ADCs suffer from inter-stage quantization noise leakage due to non-unity STF. Furthermore, improving the linearity of the multi-bit DAC often necessitates the use of mismatch error shaping (MES) or calibration techniques. Recently, continuous-time (CT) zoom ADCs have achieved inter-stage quantization noise leakage shaping by integrating noise shaping (NS) capabilities in the coarse stage [6]–[7]. Intrinsic DAC mismatch tolerance is achieved in [7] through a multi-tap FIR DAC, further streamlining the system. Nevertheless, they sacrifice the ability to scale across frequencies and their linearity and energy efficiency can be further optimized.