A 4.6-373K Functional 800MS/s 12b Buffer-then-Amplify Charge-Pump-Based Pipelined TI-SAR ADC with Integrated-Active-Hold Technique

The growing demands of cryogenic quantum computing and wide-bandwidth aerospace/automotive wireless communications have created a demand for ADC technologies capable of operating across unprecedented temperature ranges, from room temperature down to 4K, while achieving higher sampling rates and resolution. While pipelined ADC architectures offer a promising solution, their residue amplifier designs face significant challenges in wide-temperature operation, whether implemented as multi-stage closed-loop amplifiers or open-loop amplifiers (Fig. 1). The fundamental challenge lies in the dramatic device parameter variations at cryogenic temperatures, where threshold voltage (Vt) shifts by approximately 100mV and carrier mobility increases by more than 1.5x [1]. These variations create distinct limitations for existing architectures. Multi-stage closed-loop amplifiers require complex bias calibration to maintain stability [2], while open-loop amplifiers [3]–[5] suffer from large gain variations [4], necessitating an unacceptable redundancy range. Open-loop amplifiers also suffer poor linearity, which mandates a high-resolution 1 st stage SAR quantizer and leads to longer conversion times [5].

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Publication Details

Published
2025-04-13
DOI
https://doi.org/10.1109/cicc63670.2025.10983297
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
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article

A 4.6-373K Functional 800MS/s 12b Buffer-then-Amplify Charge-Pump-Based Pipelined TI-SAR ADC with Integrated-Active-Hold Technique

Hiroki Ishikuro, Kentaro Yoshioka, Вадим Іссаков, Kaoru Yamashita et al.
4 links
Analog and Mixed-Signal Circuit Design
article

A 4.6-373K Functional 800MS/s 12b Buffer-then-Amplify Charge-Pump-Based Pipelined TI-SAR ADC with Integrated-Active-Hold Technique

Hiroki Ishikuro, Kentaro Yoshioka, Вадим Іссаков, Kaoru Yamashita, Christian Ziegler
article en

Abstract

The growing demands of cryogenic quantum computing and wide-bandwidth aerospace/automotive wireless communications have created a demand for ADC technologies capable of operating across unprecedented temperature ranges, from room temperature down to 4K, while achieving higher sampling rates and resolution. While pipelined ADC architectures offer a promising solution, their residue amplifier designs face significant challenges in wide-temperature operation, whether implemented as multi-stage closed-loop amplifiers or open-loop amplifiers (Fig. 1). The fundamental challenge lies in the dramatic device parameter variations at cryogenic temperatures, where threshold voltage (Vt) shifts by approximately 100mV and carrier mobility increases by more than 1.5x [1]. These variations create distinct limitations for existing architectures. Multi-stage closed-loop amplifiers require complex bias calibration to maintain stability [2], while open-loop amplifiers [3]–[5] suffer from large gain variations [4], necessitating an unacceptable redundancy range. Open-loop amplifiers also suffer poor linearity, which mandates a high-resolution 1 st stage SAR quantizer and leads to longer conversion times [5].

Keio University (JP), Technische Universität Braunschweig (DE)
Affordable and clean energy
Openalex Percentile: Top 90%
Analog and Mixed-Signal Circuit Design
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