A 13b 2GS/s Time-Domain Pipelined ADC with Split-CDAC Ping-Pong Residue Transfer and PVT-Robust Self-Tracked Time Amplifier

High-performance RF ADCs are highly desired to relieve the design complexity in direct RF sampling receivers. The time-domain (TD) pipelined ADC is an emerging hybrid architecture benefiting from fast conversion speed and high energy efficiency [1]. Nevertheless, inter-stage residue transfer often limits its speed and linearity (Fig. 1 top). In [2], the residue voltage is transferred passively through the bottom-plate switching in coarse/fine stages by charge sharing. However, this operation costs 20% of the 1<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup>-stage timing budget, which lowers the ADC speed. Furthermore, attenuated residue voltage poses a stringent noise requirement for the backend stage. By separating quantization path and amplification path, a time-assisted residue generation scheme provides a robust voltage gain between pipelined stages [3]. While the two paths with numerous switches suffer from unbalanced parasitic and kick-back noise, limiting its linearity for a high-resolution pipelined ADC. The 1<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> stage in [3] is also slow because it needs to wait for the voltage-to-time (V2T) conversion after residue settling. To break through the speed and linearity bottlenecks, this work proposes a 3-stage TD pipelined ADC. It features non-attenuated residue transfer between the 1<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> and 2<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> stages, which removes the amplification phase in the 1<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup>-stage of conventional pipelining and accelerates the conversion speed by more than 20%. In the following stages residue transfer, a robust and self-tracked time amplifier (TA) is inserted to alleviate the backend noise requirement. The 13b TD prototype ADC running at 2GS/s achieves 62.8dB SNDR with a Nyquist input while consuming 32.2mW, leading to a Schreier FoM of 167.7dB.