A 3ns Idle-Exit Latency 0.28-28Gb/s/pin Single-Ended NRZ Die-to-Die Interface with Energy-Efficient Receiver and Background Noise Compensation

Die-to-die interfaces in high-performance computing systems demand high data transmission bandwidth, low latency, and low power consumption [1], [3]–[6]. Conventionally, current-mode, matched clocking architectures are used in high-speed transceivers for their superior jitter characteristics. However, these architectures face challenges, including latency limitations due to bias settling time and the high power consumption of current-mode circuits. To address challenges, we propose a digital-intensive, unmatched clocking architecture with background tracking schemes that compensate for power supply-induced jitter (PSIJ) at the receiver (RX) [7] and the reference mismatch between the transmitter (TX) and RX of single-ended (SE) transceiver structures [4].