A 22.0-to-28.4GHz 192.2dBc/Hz FoM and 206.2dBc/Hz FoMA Dual-Core VCO Using Circular-Inverse-Class-F Topology Under Standard Supply Voltage in 65nm CMOS Process

The demand for low-phase-noise and low-power-consumption voltage-controlled oscillators (VCOs) continues to grow, driven by the evolution of advanced applications such as 6G wireless communications and complex modulation schemes like 1024-QAM. Various techniques, including harmonic shaping and multi-core architectures, have been developed to simultaneously enhance phase noise performance and the figure-of-merit (FoM) of VCOs. However, a critical aspect often overlooked in the literature is the supply voltage. To achieve an optimal FoM, many designs employ reduced supply voltages, typically around half the standard value. While effective, integrating these designs into a complete system can be costly, as providing a unique reduced supply voltage externally is expensive. When using a non-standard supply voltage, VCOs face reliability issues unless components such as low-dropout regulators (LDOs), tail currents, or resistors are employed to control the voltage swing. These solutions, however, consume significant power-particularly when the core supply voltage is halved-and introduce noise into the VCO, thereby degrading the overall FoM. CMOS topology is another commonly used method to fit the standard supply voltage. However, the degraded performance of PMOS devices reduces the FoM in CMOS VCO. As shown in Fig. 1, a FoM gap of approximately 2 dB between standard and reduced supply voltage VCO is evident.