A 54μW Design-Agnostic Clock, Voltage, and EM-Pulse Fault-Injection Attack Detection Using Time-to-Voltage Conversion

Fault Injection Attacks (FIAs) exploit faults to reveal sensitive information or extract keys from secured crypto algorithms (e.g. AES, Kyber, ASCON) [1]–[5]. Clock, voltage, and EM pulse (EMP) based FIAs are widespread due to the availability of cheap attack hardware [4]. Such glitches exploit digital designs by creating timing failures in the data path, leading to bit-flips, stuck-at-faults, etc. [3], [4] (Fig. 1), which are exploited using algorithms such as Differential Faults Attacks [6]. In recent years, a few FIA detector ASICs have emerged, including design-specific attack detectors [7] and design-agnostic detectors[8], [9]. [7] implements an error-checking-based FIA detector for AES with a 40% area overhead. Oversampling the clock to detect glitches[8] restricts timing sensitivity and consumes high power and area (0.8mW, 4800μm2 in 5nm). [9] utilizes a delay-locked-loop (DLL) to determine the duty cycle deviation in the presence of clock glitches, consuming 300μW at 50MHz. Though [8], [9] did not include a crypto core, the power consumption of the clock-glitch detector is >50-200% of a typical crypto core (e.g. AES 256 65nm 50MHz is 590μW[10]), calling for an order-of-magnitude improvement in the power of FIA detectors. Moreover, there have been no dedicated voltage or EM Pulse glitch detector ASICs. Relying on a clock-glitch detector for voltage glitch detection, as in [9], may miss a voltage/EM Pulse glitch that creates a fault in the data path but not a clock glitch, causing true negatives.