A 24.6-to-30.6GHz Magnetic-Isolated Sub-Sampling PLL with a Fast-Locking FLL Achieving 64.9fs Jitter, −253.3dB FoM_J, and −69.1dBc Reference Spur in 65nm CMOS

With the rapid advancement of modern communication technology, communication standards have imposed stringent performance requirements on phase-locked loops (PLLs). According to the 3GPP protocol, the upper threshold for EVM is 3.5% for 256-QAM modulation, implying that the rms jitter of the local oscillation (LO) signal should be less than 100fs. Additionally, communication systems generally require the reference (REF) spur below −60dBc. Among various PLL architectures, sub-sampling PLLs (SSPLLs) exhibit superior phase noise and jitter performance. However, due to the sub-sampling operation, the voltage-controlled oscillator (VCO) experiences periodic disturbances, leading to a high REF spur. The REF spur is mainly introduced by the binary frequency-shift-keying (BFSK), charge injection, and charge sharing effects, as illustrated in Fig. 1 (top). To mitigate these issues, a dummy sampling path is introduced [1] (Fig. 1 bottom left), ideally providing a constant capacitive load to the VCO tank and eliminating the BFSK effect. In practice, however, mismatches between the main and dummy paths significantly degrade the REF spur. Instead of directly connecting the sampling circuit to the VCO tank, the isolated-sub-sampling PLL (iSSPLL) [2] employs a transistor (i.e., Mi) to minimize disturbances from the sampling circuit on the VCO core (Fig. 1 bottom middle). However, this topology introduces a trade-off between REF spur and phase noise. Specifically, increasing the size of Mi enhances the gain in the sub-sampling phase detector (SSPD), which helps suppress in-band noise, but it also increases the parasitic capacitance (i.e., C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</inf>), thereby worsening the REF spur. To counteract this issue, [3] adopts a function-reused (FR) VCO-buffer to mitigate the noise and capacitive loading from the VCO-buffer transistors, improving the REF spur to −66dBc. Nevertheless, the load resistor R<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</inf> within the FR VCO-buffer introduces an additional voltage drop, leading to higher power consumption (17mW). Beyond REF spur concern, SSPLLs are also prone to incorrect frequency locking and external disturbances, necessitating the integration of a frequency locking loop (FLL) with a dead zone (DZ) of [-π, π] to ensure the correct frequency output. Exiting the DZ requires a significant long-time accumulation of phase error, thereby prolonging the overall locking time of the SSPLL [1]. To shorten this locking time and enhance robustness, automatic soft switching between the sub-sampling phase loop and frequency loop is proposed in [4], realizing a DZ of approximately [-π/2, π/2]. However, this approach requires off-chip calibration for the switch threshold voltage. A quadrature SSPD-based DZ automatic controller is also an effective way to shorten the locking time [5], but the quadrature divider consumes substantial power (4.1mW) to generate the necessary quadrature signals.