A 22.4-25.6GHz Ping-Pong Sub-Sampling PLL Featuring Unified Supply Voltage and Balanced 2^nd Harmonic Extraction Achieving 45.8fs_rms Jitter and -254.3dB FoM

Emerging ultra-high-speed wireless and wireline transceivers keep posing stringent jitter requirements on local millimeter-wave (mm-wave) clock generators [1]. Sub-sampling PLLs (SS-PLLs) [2]–[7] are the most popular architecture for low-jitter mm-wave clock generation due to the inherent high phase-detection gain (KPD) and elimination of the high-frequency divider. Yet, direct mm-wave voltage-controlled oscillators (VCOs) suffer from inferior phase noise (PN) resulting from severe capacitor Q-factor degradation, thus limiting the overall PLL jitter performance. Alternatively, the indirect mm-wave clock generation can mitigate the Q-factor degradation effect through harmonic extraction techniques [8]–[10] (Fig. 1, top). Yet, such architectures require multi-stage power- and area-hungry amplifier-based buffers to amplify the harmonic amplitude and filter the fundamental component, which in turn reduces the advantages of harmonic-extraction PLLs. Another critical but seldom discussed aspect in prior PLL designs is the unification of the supply voltage (VDD). The usual utilization of a lower than nominal system VDD for the NMOS VCO and harmonic buffers optimizes the PN performance and avoids overly-Iarge-swing-induced reliability issues. In this case, additional low-dropout regulators (LDOs) are inevitably necessary for the complete system integration of the entire PLL [11], degrading the overall jitter-power figure-of-merit (FoM).