A Power-Efficient Jitter-Insensitive 3.2GHz 1-bit CT ΔΣ ADC with Direct Charge Dump Feedback
Using a 1-bit quantizer (QTZ) in a multi-GHz CT <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta\Sigma$</tex> ADC is beneficial as a 1-bit DAC demands no mismatch calibration or DEM. Additionally, a 1-bit QTZ is simple, does not require offset calibration, and easy to drive. However, in a CT <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta\Sigma$</tex> ADC using an active RC integrator and a resistive/current-steering (R/I) 1-bit feedback (FB) (Fig. 1, top-left), OTA 1 needs to absorb the large feedback current <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$I_{\text{fb}}$</tex>, which dictates OTA 1's power [1]. Moreover, a 1-bit <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{R}/$</tex> I FB is sensitive to jitter. An FIR FB reduces <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{I}_{\text{fb}}$</tex> and jitter sensitivity [2], but suffers from inter-symbol interference (ISI). A time-interleaved (TI) FIR FB can address the ISI issue [3], but the calibration demand of gain mismatches among TI DAC slices erases the benefit of the mismatch-calibration/DEM free characteristic of a 1-bit DAC. Alternatively, switched capacitor (SC) FB can be used to suppress both jitter impact and ISI by feeding a packet of charge to the loop filter (LF) in an impulsive manner [4]. However, OTA1 needs to absorb the resulting high peak current (Fig. 1, top-right), which consumes more power than that with a R/I FB. Mainly due to the power-hungry OTA 1, Schreier FoM (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{FoM}_{\mathrm{S}})$</tex> of the state-of-the-art 1-bit, DAC-calibration/DEM-free CT <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta\Sigma$</tex> ADCs with the conventional FBs is below 165dB [1], [5], [6] while multi-bit CT <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta \Sigma$</tex> ADCs have achieved <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{FoM}_{\mathrm{S}}$</tex> beyond 170dB [7] [8].
Authors
- Yanquan Luo (ORCID: https://orcid.org/0000-0003-1057-2996)
- Lu Jie (ORCID: https://orcid.org/0000-0001-5046-3917)
- Nan Sun (ORCID: https://orcid.org/0000-0001-9689-3250)
Institutions
- Tsinghua University (CN)
Publication Details
- Published
- 2025-04-13
- DOI
- https://doi.org/10.1109/cicc63670.2025.10982938
- Citations
- 2
- Primary Topic
- Analog and Mixed-Signal Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 1.35