16 Arrays of 32 All-to-All Coupled CMOS Oscillators for AI Inference and Combinatorial Optimization

With rapid advancement of computing tasks, like artificial intelligence (AI), combinatorial optimization problems (COPs), scientific computing and so on, significant improvement of energy efficiency is becoming more critical. Analog computing has been actively explored [1] and is expected to be more efficient than general purpose computing. It can handle one of the key unavoidable operations, matrix multiplication. As shown in Fig. 1, oscillators coupled via an averager node, where its voltage envelop signal (also called degree of match, DoM) correlates to oscillator frequency variance. The input and weight will determine the initial frequency of each oscillator by varying its iDAC code based on input (I) minus weight (W) for each of matrix element. This mechanism can help calculate dot products efficiently. As both AI inference and NP-hard Ising problems can be transformed into a series of matrix multiplications, the same oscillator hardware can manage these two different tasks. Previous work validated synchronization in a single CMOS coupled-oscillator array and its analog output [2], but no end-to-end processing or scalability has been shown. In this paper, a demonstration of a 16-array CMOS coupled-oscillator system with digitized input / output, performing AI inference as well as NP-hard Travelling Salesman Problem (TSP), is presented.

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Published
2025-04-13
DOI
https://doi.org/10.1109/cicc63670.2025.10983669
Primary Topic
Analog and Mixed-Signal Circuit Design
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article
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article

16 Arrays of 32 All-to-All Coupled CMOS Oscillators for AI Inference and Combinatorial Optimization

Y. Fan, James Ayers, Hai Li, Dmitri E. Nikonov et al.
Analog and Mixed-Signal Circuit Design
article

16 Arrays of 32 All-to-All Coupled CMOS Oscillators for AI Inference and Combinatorial Optimization

Y. Fan, James Ayers, Hai Li, Dmitri E. Nikonov, Anni Lu, Ian A. Young, You Li
article en

Abstract

With rapid advancement of computing tasks, like artificial intelligence (AI), combinatorial optimization problems (COPs), scientific computing and so on, significant improvement of energy efficiency is becoming more critical. Analog computing has been actively explored [1] and is expected to be more efficient than general purpose computing. It can handle one of the key unavoidable operations, matrix multiplication. As shown in Fig. 1, oscillators coupled via an averager node, where its voltage envelop signal (also called degree of match, DoM) correlates to oscillator frequency variance. The input and weight will determine the initial frequency of each oscillator by varying its iDAC code based on input (I) minus weight (W) for each of matrix element. This mechanism can help calculate dot products efficiently. As both AI inference and NP-hard Ising problems can be transformed into a series of matrix multiplications, the same oscillator hardware can manage these two different tasks. Previous work validated synchronization in a single CMOS coupled-oscillator array and its analog output [2], but no end-to-end processing or scalability has been shown. In this paper, a demonstration of a 16-array CMOS coupled-oscillator system with digitized input / output, performing AI inference as well as NP-hard Travelling Salesman Problem (TSP), is presented.

Intel (United States) (US)
Openalex Percentile: Top 90%
Analog and Mixed-Signal Circuit Design
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