A 4.6-6GHz Self-Injection LC Oscillator Exploiting 2^nd Harmonic Extraction and Self-Mixing to Achieve 5-35kHz 1/f³ Phase Noise Corner and 201dB FoMT

Frequency synthesizers for high-performance wireless and wireline applications require an integrated RMS jitter of <200fs. The total phase noise (PN) of the synthesizer is a tradeoff between the reference and VCO PN with respect to the loop bandwidth. To achieve <200fs jitter, apart from reducing the 1/f2 PN, it becomes crucial to reduce the 1/f3 PN corner [1]. This is especially needed for a lowbandwidth type-II PLL or a type-I PLL where the VCO PN shaping is relatively weaker. For instance, simulation results indicate that the total integrated jitter of a type-II subsampling PLL operating at 2.5GHz with a 15kHz loop bandwidth and a realistic 100 MHz reference can be reduced from 200 to 145fs when the VCO's 1/f3 phase noise corner is lowered from 300 to 1kHz, assuming the same 1/f2 phase noise performances for the two cases.