A 32GS/s 8b 16× Time-Interleaved Hybrid ADC with Self-Detection Offset Calibration, DLL-Based T_LSB PVT Variation Calibration and VTC Gain Self-Tracking

ADC-DSP-Based PAM-4 long-reach transceivers are a key enabler for the ever-increasing data throughput demands of generative Al. A higher input bandwidth in these applications necessitates the embedded time-interleaved (TI) ADCs operating at several to tens of GS/s with at least 5 ENOB. Since input signals are orderly distributed across the enormous parallel sub-channels, the sub-ADCs should offer a high sampling rate and efficiency in both area and power. The voltage-domain SAR-based sub-ADCs are a proven power-efficient architecture [1]–[4]. However, ultra-high-speed TI-SARs with an enormous interleaving factor suffer from the long interconnection routing lines, limiting the effective bandwidth. Recently, time-domain (TD) ADCs have shown promising speed features with a compact layout due to the highly digital structure [5], [6]. However, the inverter-based time-quantization step (T <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LSB</inf>) introduces PVT variations and mismatch issues, which are exacerbated in interleaved ADCs. It also poses a challenge for the voltage-to-time converter (VTC) to track the gain error caused by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{T}_{\text{LSB}}$</tex> variations. Thus, efficient and practical calibration mechanisms are essential for TI TD-ADCs to fully exploit the speed advantages of time-domain operation. A Tl hybrid SAR+ TDC with three on-chip calibrations is presented in this work. Inspired by the multi-phase clock generation scheme [7], [8], the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{T}_{\text{LSB}}$</tex> variation can be calibrated by a delay-locked loop (DLL). Furthermore, a pulse tracking loop is proposed to tune the conversion gain of the VTC. As for TI hybrid SAR+ TDCs, an offset mismatch calibration is embedded in the first-stage SAR ADC to capture and compensate for the offset mismatch contributed by the hierarchical sampler and comparator. It is worth noting that these techniques perform detection and compensation entirely in the analog domain. A proof-of-concept ADC prototype in 28 nm CMOS technology with 16× time interleaving achieves 32 GS/s with 36.0 dB SNDR at Nyquist frequency. The ENOB stays above 5 bits up to 20 GHz input. The proposed calibration technique makes the TI hybrid SAR+ TDC robust to temperature and voltage variations.