A 12.5GS/s 14.7mW 4×TI Pipelined Hybrid TD-SAR ADC with Residual Time-Voltage Amplification

With the development of wireline communication systems, the demand for ultra-high speed (exceeding 10GS/s) and moderate-resolution ADCs has grown rapidly. The voltage-domain (VD) time-interleaved (TI) SAR ADC [1]–[5] with a large number of interleaving factors is the conventional mainstream choice, but it requires a lot of overhead in the area and drives large input loading. TI time-domain (TD) ADCs with a fast single-channel speed (≥2.5GS/s) [6]–[11] can significantly reduce the number of channels, but their thermometer code-based quantization causes the number of transistors to grow exponentially with the resolution. As shown in Figure 1 (top), the prior TD ADCs [6] [8] need to generate a sub-gate delay step (T LSB) to minimize the 8-bit time range <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(2^{8}\times \mathrm{T}_{\text{LSB}})$</tex>. [6] proposes a complicated and power-hungry 16× interpolation-based time-to-digital converter (TDC) to generate 1.4ps fine delay, and [8] proposes a tuning-based SAR TDC with 0.5ps fine delay suffering from clock jitter noise and depending on the accurate tuning of delay difference. In the hybrid TD-VD ADCs [12]–[14] shown in Figure 1 (middle), the voltage-to-time converter (VTC) converts the input signal to the time-domain at first, then the time-to-voltage converter (TVC) converts the time signal to the voltage-domain again, and it allows high-speed TDCs to perform MSB quantization simultaneously. Next, the voltage signal on the (M+N-1) bits CDAC is converted to the voltage residue by feeding MSBs back. Finally, the TI-SAR is used for LSB quantization to replace the fine TDC in [6] [8]. Therefore, the hybrid architecture can balance the advantages of high speed in TD ADCs and excellent energy efficiency in SAR ADCs. However, the M-bit TDC and N-bit SAR employ sub-ranging, resulting in a small input swing <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\leq 100\text{mV}_{\text{PP}})$</tex> [13] [14] of the SAR, which will limit the speed of SAR conversion significantly, especially for the LSBs. The (M+N-1) bits CDAC imposes a large load on TVC and SAR conversion, which consumes a large power.