A 1.8V Input, 96.5% Efficiency, 4.05A/mm² FoM, Three-Level Dual-Path Hybrid Buck Converter with Mitigated Capacitive Inrush Current and Seamless DVS Across a Wide 0.4-to-1.5V Output Range

Modern mobile SoCs increasingly demand energy-efficient, high-density power converter solutions that employ compact passive components within a small footprint, while still delivering sufficient power and retaining high efficiency. To meet these requirements, flying capacitor <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(C_{\mathrm{F}})$</tex> -assisted hybrid buck converters have been extensively explored as a viable option to reduce conduction losses <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(P_{\mathrm{D}\mathrm{C}\mathrm{R}})$</tex> associated with the higher DC resistance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(R_{\mathrm{D}\mathrm{C}\mathrm{R}})$</tex> of miniaturized inductors [1]–[7]. In these hybrid designs, the reduction of inductor current <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(/_{\mathrm{L}})$</tex>-thereby <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$P_{\mathrm{D}\mathrm{C}\mathrm{R}}(=R_{\mathrm{D}\mathrm{C}\mathrm{R}}\cdot I_{\mathrm{L}^{2}})$</tex> minimization-is achieved by leveraging the current contribution from the flying capacitor <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(I_{\mathrm{C}\mathrm{F},\mathrm{C}}$</tex> to support power delivery alongside <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$I_{\mathrm{L}}$</tex>. However, a significant challenge remains: efficiency degradation due to surged <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$I_{\mathrm{C}\mathrm{F},\mathrm{C}}$</tex> at specific voltage conversion ratios (VCRs). To mitigate this, [8] proposed an interleaved topology to relieve inrush <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$I_{\mathrm{C}\mathrm{F},\mathrm{C}}$</tex>, while [9] introduced a switched-capacitor design methodology optimized for a target VCR. Despite these advancements, their theoretical VCR limitations <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(M=V_{\mathrm{O}} / V_{\text{IN}}&gt;0.5$</tex> in [8], <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$M &lt; 0.4$</tex> in [9]) restrict supplying SoC-compatible voltages from a 1.8V input <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(0.22\ &lt; M &lt; 0.83)$</tex>. Recent research has thus focused on alleviating inrush <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$I_{\mathrm{C}\mathrm{F},\mathrm{C}}$</tex> while covering a wider VCR range [10], [11]. Following this trend, this paper proposes a three-level dual-path (TLDP) hybrid buck converter that seamlessly operates across a broad VCR range <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(V_{1\text{IN}} =1.8, V_{\mathrm{O}}=0.4$</tex> to 1.5V) while effectively mitigating <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$I_{\mathrm{C}\mathrm{F},\mathrm{C}}$</tex> surges. In contrast to [10], which tends to be inefficient at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$M=0.5$</tex> in terms of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$I_{\mathrm{L}}$</tex> -reduction, the proposed TLDP design maximizes the benefits of multi-path power delivery at mid-range VCRs <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(M\approx 0.5)$</tex>, commonly used to power SoCs with typical <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{\text{DD}}$</tex> ranging from 0.6 to 1.2V.