A Fully Integrated Adaptive-MPP-Shifting Rectifier for Piezoelectric Energy Harvesting Outputting 580µW at 10V-V_OC

Piezoelectric energy harvesting (PEH) has become a promising alternative to conventional batteries for powering wireless sensors and edge computing devices. Among various rectifier topologies for PEH, synchronized bias-flip rectifiers, such as parallel synchronized switch harvesting on inductor (SSHI) [1] and capacitors (SSHC) rectifiers [2], have garnered significant attention in recent years due to their higher output power if the optimal output voltage is reached. A typical structure of a bias-flip rectifier and its output power related to the rectifier's output voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">REC</inf>) are shown in Fig. 1 (left). As the VREC changes, a distinctive peak power exists, signifying the maximum power point (MPP) [3]–[5]. At this point, VREC is at its optimal value, expressed by V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MPP</inf>= <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{Voc}/(1-\mathrm{q}_{\mathrm{F}}).\text{Voc}$</tex> is the open circuit voltage amplitude of a piezoelectric transducer (PT), typically between 1 V and 10V under most real-world excitation levels, and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\eta_{\mathrm{F}}$</tex> is the flipping efficiency of a bias-flip rectifier. To track and maintain the rectifier's output power at the MPP, an MPPT (Maximum Power Point Tracking) block is needed after the rectifier to regulate V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">REC</inf>. While most prior designs have been mainly focused on increasing <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\eta_{\mathrm{F}}$</tex>, usually over 60%, for greater output power [6]–[16], the theoretical V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MPP</inf> can easily go higher than the breakdown voltage (5V) of standard CMOS devices if V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OC</inf> is higher than 2V. As a result, the reachable MPP still stays at 5V to protect the chip, with a much lower output power than the theoretical MPP. Though LDMOS devices allow VREC to track higher V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MPP</inf>, the resulting high V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">REC</inf> introduces high-voltage pressures and large voltage step-down ratios for the following power-conditioning stages. This has been an unsolved challenge limiting the output power of all CMOS bias-flip rectifiers since it was first introduced at ISSCC'2009 [1].