A 100Gb/s Transmitter with Digital Pre-Distortion and MUX-Merged Voltage-Mode Driver Achieving 3-Times INL<sub>PP</sub> Improvement in 28nm CMOS
In high-speed wireline transmitters (TXs), the output drivers are mainly categorized into two types, i.e., current-mode logic (CML) and voltage-mode (VM) driver. For TXs with data rates exceeding 100Gb/s, most of existing work resorts to the CML driver for higher bandwidth [1]–[6]. Although VM driver consumes less power for the same output swing and exhibits good technology scalability, its output impedance is significantly affected by the source-drain voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</inf>) of MOSFETs, resulting in poor linearity, especially for PAM-4 signaling. Additionally, the timing margin between retiming clock and data in TX may fail to meet the constraint due to PVT variations [7].
Authors
- Xiaoteng Zhao (ORCID: https://orcid.org/0000-0002-9447-8763)
- Chenxi Han (ORCID: https://orcid.org/0000-0003-4053-5897)
- Lianxi Liu (ORCID: https://orcid.org/0000-0002-9897-5361)
- Hongzhi Liang (ORCID: https://orcid.org/0000-0001-6609-9486)
- Yuhao Zhang (ORCID: https://orcid.org/0000-0001-7325-6507)
- Qi Zhang (ORCID: https://orcid.org/0000-0002-6030-1791)
- Yuan Liu (ORCID: https://orcid.org/0000-0002-8880-3451)
- Zhangming Zhu (ORCID: https://orcid.org/0000-0003-4750-5922)
- Yukui Yu
Institutions
- Xidian University (CN)
Publication Details
- Published
- 2025-04-13
- DOI
- https://doi.org/10.1109/cicc63670.2025.10983867
- Primary Topic
- Advancements in PLL and VCO Technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- National Natural Science Foundation of China
- National Key Research and Development Program of China