BASS-PLL: A Bandwidth Augmented Sub-Sampling PLL Achieving a Wide Bandwidth Above 30% of the Reference Frequency and a Worst Case FoM<sub>REF</sub> of -247.9dB at 3GHz with a Ring Oscillator

Applications such as multilane wireline links and multistream radios often require multiple low-area/cost frequency synthesizers, which motivates the use of ring-oscillator (RO)-based PLLs. However, the phase noise and jitter performance of RO-PLLs are often not sufficient to support the needs of these high-performance applications due to the high RO phase noise. Reference over-sampling PLLs (OS-PLLs), illustrated in Fig. 1 (top left), can help reduce the impact of RO noise by oversampling the reference, leading to increased loop bandwidth and suppressed out-of-band RO noise [1]. However, the achievable sampling gain is limited by the reference frequency, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{f}_{\text{REF}}$</tex>, which is typically ≤100 MHz for practical crystal references, and, frustratingly, sampling gain also varies within a single reference period - even approaching zero near the peak of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{REF}}$</tex> - leading to dynamically-varying loop bandwidths, deteriorated stability, and limited ability to suppress in-band noise contributors. Sub-sampling PLLs (SS-PLLs, Fig. 1 top right) [2], on the other hand, are known to have high intrinsic sampling gain by directly sampling the VCO's output, and as a result can achieve excellent in-band noise suppression, though total noise is still dominated by the RO. While techniques such as dual-path sub-sampling [3], concurrent proportional/integral gain optimization [4], cascaded DLL/RO high frequency noise suppression [2], time-based active loop filtering [5], and multi phase generator based injection locked clock multipliers (ILCM) [6], [7] can be used to suppress RO phase noise, the drastically increased power and area overhead, calibration complexity in mitigating the deteriorated spur performance, and difficulty in stabilizing their operation in these methods tend to constrain the feasible extension of loop bandwidth for RO suppression.

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Published
2025-04-13
DOI
https://doi.org/10.1109/cicc63670.2025.10983164
Citations
3
Primary Topic
Advancements in PLL and VCO Technologies
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article
Field-Weighted Citation Impact
2.19
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article

BASS-PLL: A Bandwidth Augmented Sub-Sampling PLL Achieving a Wide Bandwidth Above 30% of the Reference Frequency and a Worst Case FoMREF of -247.9dB at 3GHz with a Ring Oscillator

Honglan Jiang, Deyong Li, Patrick P. Mercier, Wan Qi Jie et al.
3 citations
Advancements in PLL and VCO Technologies
2.19
article

BASS-PLL: A Bandwidth Augmented Sub-Sampling PLL Achieving a Wide Bandwidth Above 30% of the Reference Frequency and a Worst Case FoMREF of -247.9dB at 3GHz with a Ring Oscillator

Honglan Jiang, Deyong Li, Patrick P. Mercier, Wan Qi Jie, Xueke Cai, Tong Zhang, Hui Wang, Yongfu Li, Yang Zhao, Yanling Zheng, Yiwen Zhang
article en
3 citations

Abstract

Applications such as multilane wireline links and multistream radios often require multiple low-area/cost frequency synthesizers, which motivates the use of ring-oscillator (RO)-based PLLs. However, the phase noise and jitter performance of RO-PLLs are often not sufficient to support the needs of these high-performance applications due to the high RO phase noise. Reference over-sampling PLLs (OS-PLLs), illustrated in Fig. 1 (top left), can help reduce the impact of RO noise by oversampling the reference, leading to increased loop bandwidth and suppressed out-of-band RO noise [1]. However, the achievable sampling gain is limited by the reference frequency, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{f}_{\text{REF}}$</tex>, which is typically ≤100 MHz for practical crystal references, and, frustratingly, sampling gain also varies within a single reference period - even approaching zero near the peak of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{REF}}$</tex> - leading to dynamically-varying loop bandwidths, deteriorated stability, and limited ability to suppress in-band noise contributors. Sub-sampling PLLs (SS-PLLs, Fig. 1 top right) [2], on the other hand, are known to have high intrinsic sampling gain by directly sampling the VCO's output, and as a result can achieve excellent in-band noise suppression, though total noise is still dominated by the RO. While techniques such as dual-path sub-sampling [3], concurrent proportional/integral gain optimization [4], cascaded DLL/RO high frequency noise suppression [2], time-based active loop filtering [5], and multi phase generator based injection locked clock multipliers (ILCM) [6], [7] can be used to suppress RO phase noise, the drastically increased power and area overhead, calibration complexity in mitigating the deteriorated spur performance, and difficulty in stabilizing their operation in these methods tend to constrain the feasible extension of loop bandwidth for RO suppression.

Shanghai Jiao Tong University (CN), University of California San Diego (US)
Openalex Percentile: Top 12%
Advancements in PLL and VCO Technologies
2.19
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