A 16nm 140-fJ/b/dB Dual-Mode ENRZ/NRZ Serial Data Transceiver with Dynamic Voltage Scaling

A dual-mode long-reach serial data transceiver supporting both Non-Return to Zero (NRZ) and Ensemble NRZ (ENRZ) signaling schemes is presented. Low power dissipation, compatibility with the conventional design architectures, low sensitivity to Inter-Symbol Interference (ISI), and maintaining a high level of signal integrity are the key aspects of the proposed ENRZ link. Supporting USB and Display Port (DP) [1], [2] standards in NRZ mode, the ENRZ mode has been added as a test option to demonstrate the capability of ENRZ signaling to enhance the link throughput by 50% at the same baud-rate as NRZ, without compromising signal integrity, while enhancing energy-efficiency. Implemented in 16 nm FinFET, the proposed link covers Nyquist channel losses ranging from 6 dB up to 28 dB, with a BER better than 1 E-13 when operating at 20 Gbaud, i.e., 10 Gb/s/wire (NRZ) and 15 Gb/s/wire (ENRZ).

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Publication Details

Published
2025-04-13
DOI
https://doi.org/10.1109/cicc63670.2025.10982712
Primary Topic
VLSI and Analog Circuit Testing
Type
article
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article

A 16nm 140-fJ/b/dB Dual-Mode ENRZ/NRZ Serial Data Transceiver with Dynamic Voltage Scaling

Patryk J. Urban, Milad Ataei, Giuseppe Surace, D. Stauffer et al.
1 links
VLSI and Analog Circuit Testing
article

A 16nm 140-fJ/b/dB Dual-Mode ENRZ/NRZ Serial Data Transceiver with Dynamic Voltage Scaling

Patryk J. Urban, Milad Ataei, Giuseppe Surace, D. Stauffer, James Hudner, Armin Tajalli, Kiarash Gharibdoust, Amin Shokrollahi, Victor Perrin, Cosimo Aprile, Andrew Stewart, Ali Hormati, R. S. Simpson, Roger Ulrich, Anant Singh, Mark Venneborger, Rolf Beerwerth, Dario Carneli, Maik Fuhs
article en

Abstract

A dual-mode long-reach serial data transceiver supporting both Non-Return to Zero (NRZ) and Ensemble NRZ (ENRZ) signaling schemes is presented. Low power dissipation, compatibility with the conventional design architectures, low sensitivity to Inter-Symbol Interference (ISI), and maintaining a high level of signal integrity are the key aspects of the proposed ENRZ link. Supporting USB and Display Port (DP) [1], [2] standards in NRZ mode, the ENRZ mode has been added as a test option to demonstrate the capability of ENRZ signaling to enhance the link throughput by 50% at the same baud-rate as NRZ, without compromising signal integrity, while enhancing energy-efficiency. Implemented in 16 nm FinFET, the proposed link covers Nyquist channel losses ranging from 6 dB up to 28 dB, with a BER better than 1 E-13 when operating at 20 Gbaud, i.e., 10 Gb/s/wire (NRZ) and 15 Gb/s/wire (ENRZ).

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VLSI and Analog Circuit Testing
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